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| INTEGRATED CIRCUITS DATA SHEET TZA3017HW 30-3200 Mbits/s fibre optic transmitter Objective specification File under Integrated Circuits, IC19 2002 Jan 16 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter FEATURES * Single 3.3 V power supply * 1.5 W maximum power dissipation * Supports SDH/SONET rates at 155.52, 622.08 and 2488.32 Mbits/s (including STM16/OC48 + FEC) * Supports Gigabit Ethernet at 1250 and 3125 Mbits/s * Supports Fibre Channel at 1062.5 and 2125 Mbits/s * 16 : 1, 8 : 1 or 4 : 1 multiplexing ratio * 10 : 1 multiplexing ratio for 8B/10B encoded protocols (e.g. Gigabit Ethernet) * Rail-to-rail parallel inputs compliant with Positive Emitter Coupled Logic (PECL), Current-Mode Logic (CML) and Low Voltage Differential Signalling (LVDS) * Supports co-directional and contra-directional clocking * 4-stage FIFO providing large jitter tolerance on parallel interface * Parity error detect, with programmable parity (odd or even) * Loss Of Lock (LOL) indicator * ITU-T compliant jitter generation * CML data and clock outputs * CML data and clock inputs for line loop back * CML data and clock outputs for diagnostic loop back * I2C-bus programmable. Additional features with the I2C-bus * Supports any line rate from 30 Mbits/s to 3.2 Gbits/s * Programmable frequency resolution of 10 Hz * Adjustable swing for CML data and clock outputs * Adjustable polarity of all RF I/Os * Clock versus data swap for optimum connectivity * Programmable parallel bus order for optimum connectivity * Adjustable LVPECL or CML output swing * Reference frequency divide by 1, 2, 4 or 8. GENERAL DESCRIPTION TZA3017HW APPLICATIONS * Any optical transmission system with line rates between 30 Mbits/s and 3.2 Gbits/s * Physical interface IC in transmit channels * Transponder applications * Dense Wavelength Division Multiplexing (DWDM) systems. The TZA3017HW is a highly integrated optical network transmitter, comprising a clock synthesizer and a 16 : 1, 8 : 1 or 4 : 1 multiplexer (10 : 1 for 8B/10B encoded signals). The IC operates at any line rate between 30 Mbits/s and 3.2 Gbits/s. Additional RF inputs and outputs for loop mode connections are present. Using the I2C-bus gives the product a high configuration flexibility. The HTQFP100 package has excellent electrical and thermal properties. ORDERING INFORMATION TYPE NUMBER TZA3017HW PACKAGE NAME HTQFP100 DESCRIPTION plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm VERSION SOT638-1 2002 Jan 16 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Jan 16 OVERFLOW FIFORESET PARERR PARERRQ PARINV PARITY PARITYQ D00 to D15 55 56 74 73 44 38 37 16 4, 6, 8, 10, 12, 15, 17, 19, 21, 23, 28, 30, 32, 95, 97, 99 D00Q to D15Q 16 3, 5, 7, 9, 11, 14, 16, 18, 20, 22, 27, 29, 31, 94, 96, 98 PICLK PICLKQ 35 34 W R PARITY CHECKER AND BUS SWAP 16 16 D C 2 67 66 60 4 deep FIFO 16 16 MUX 4:1 8:1 10 : 1 16 : 1 2 2 2 D C 2 89 88 92 91 85 86 52 2 CLKDIR POCLK POCLKQ 71 40 39 0 / 90 PHASE SHIFT 2 1, 25, 33, 36, 41, 49, 58, 61, 64, 65, 68, 77, 80, 83, 87, 90, 93, 100 57 48 47 43 42 18 MD0 MD1 PRSCLO LOL CREF VCCD VCCA VCCO VDD 75 69 51 2 CLOCK SYNTHESIZER POWER-ON RESET I2C-BUS 53 54 72 DLOOP DLOOPQ CLOOP CLOOPQ ENLOUTQ ENLINQ SCL(DR2) SDA(DR1) CS(DR0) UI 59 BLOCK DIAGRAM Philips Semiconductors handbook, full pagewidth 30-3200 Mbits/s fibre optic transmitter MUXR1 MUXR0 46 CINQ 45 CIN DINQ 82 DIN 81 78 79 INTERRUPT CONTROLLER 84 INT DOUT DOUTQ COUT COUTQ 3 2 TZA3017HW 62 63 2, 13, 24, 26, 50, 70, 76 7 VEE MGW559 Objective specification TZA3017HW PRSCLOQ CREFQ Fig.1 Simplified block diagram. Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter PINNING SYMBOL VCCD VEE D12Q D12 D11Q D11 D10Q D10 D09Q D09 D08Q D08 VEE D07Q D07 D06Q D06 D05Q D05 D04Q D04 D03Q D03 VEE VCCD VEE D02Q D02 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ground inverted parallel data input; bit 12 non-inverted parallel data input; bit 12 inverted parallel data input; bit 11 non-inverted parallel data input; bit 11 inverted parallel data input; bit 10 non-inverted parallel data input; bit 10 inverted parallel data input; bit 9 non-inverted parallel data input; bit 9 inverted parallel data input; bit 8 non-inverted parallel data input; bit 8 ground inverted parallel data input; bit 7 non-inverted parallel data input; bit 7 inverted parallel data input; bit 6 non-inverted parallel data input; bit 6 inverted parallel data input; bit 5 non-inverted parallel data input; bit 5 inverted parallel data input; bit 4 non-inverted parallel data input; bit 4 inverted parallel data input; bit 3 non-inverted parallel data input; bit 3 ground supply voltage (digital part) ground inverted parallel data input; bit 2 non-inverted parallel data input; bit 2 VCCD VEE VDD SCL(DR2) SDA(DR1) CS(DR0) OVERFLOW FIFORESET LOL VCCD COUTQ COUT VCCD MD0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 VCCD CREFQ CREF PARINV MUXR1 MUXR0 PRSCLOQ PRSCLO 41 42 43 44 45 46 47 48 D00Q D00 VCCD PICLKQ PICLK VCCD PARITYQ PARITY POCLKQ POCLK 31 32 33 34 35 36 37 38 39 40 DESCRIPTION supply voltage (digital part) TZA3017HW SYMBOL D01Q D01 PIN 29 30 DESCRIPTION inverted parallel data input; bit 1 non-inverted parallel data input; bit 1 inverted parallel data input; bit 0 non-inverted parallel data input; bit 0 supply voltage (digital part) inverted parallel clock input non-inverted parallel clock input supply voltage (digital part) inverted parity input non-inverted parity input inverted parallel output clock non-inverted parallel output clock supply voltage (digital part) inverted reference clock input non-inverted reference clock input parity invert input (odd or even) select MUX ratio select MUX ratio inverted prescaler output signal non-inverted prescaler output signal supply voltage (digital part) ground supply voltage (digital part) I2C-bus serial clock (data rate select 2) I2C-bus serial data (data rate select 1) chip select (data rate select 0) FIFO overflow alarm output FIFO reset input loss of lock output supply voltage (digital part) inverted serial clock output non-inverted serial clock output supply voltage (digital part) parallel data input termination mode select 2002 Jan 16 4 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW SYMBOL MD1 VCCD VCCD DOUTQ DOUT VCCD VCCO VEE CLKDIR UI PARERRQ PARERR VCCA VEE VCCD DINQ DIN VCCD CINQ CIN VCCD INT PIN 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DESCRIPTION parallel data input termination mode select supply voltage (digital part) supply voltage (digital part) inverted serial data output non-inverted serial data output supply voltage (digital part) supply voltage (clock generator) ground selection between co- and contra-directional input timing user interface selection inverted parity error output non-inverted parity error output supply voltage (analog part) ground supply voltage (digital part) inverted loop mode data input non-inverted loop mode data input supply voltage (digital part) inverted loop mode clock input non-inverted loop mode clock input supply voltage (digital part) interrupt output SYMBOL ENLOUTQ ENLINQ VCCD DLOOPQ DLOOP VCCD CLOOPQ CLOOP VCCD D15Q D15 D14Q D14 D13Q D13 VCCD VEE PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 die pad DESCRIPTION enable diagnostic loop back (active LOW) enable line loop back (active LOW) supply voltage (digital part) inverted loop mode data output non-inverted loop mode data output supply voltage (digital part) inverted loop mode clock output non-inverted loop mode clock output supply voltage (digital part) inverted parallel data input; bit 15 non-inverted parallel data input; bit 15 inverted parallel data input; bit 14 non-inverted parallel data input; bit 14 inverted parallel data input; bit 13 non-inverted parallel data input; bit 13 supply voltage (digital part) common ground plane 2002 Jan 16 5 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW 91 CLOOPQ 88 DLOOPQ handbook, full pagewidth 100 VCCD 99 D13 85 ENLOUTQ 86 ENLINQ 93 VCCD 92 CLOOP 90 VCCD 89 DLOOP 87 VCCD 83 VCCD 82 CIN 80 VCCD 79 DIN VCCD VEE D12Q D12 D11Q D11 D10Q D10 D09Q 77 VCCD 76 VEE 75 VCCA 74 PARERR 73 PARERRQ 72 UI 71 CLKDIR 70 VEE 69 VCCO 68 VCCD 67 DOUT 66 DOUTQ 65 VCCD 64 VCCD 63 MD1 62 MD0 61 VCCD 60 COUT 59 COUTQ 58 VCCD 57 LOL 56 FIFORESET 55 OVERFLOW 54 CS(DR0) 53 SDA(DR1) 52 SCL(DR2) 51 VDD VCCD 49 VEE 50 98 D13Q 96 D14Q 94 D15Q 81 CINQ 1 2 3 4 5 6 7 8 9 D09 10 D08Q 11 D08 12 VEE 13 D07Q 14 D07 15 D06Q 16 D06 17 D05Q 18 D05 19 D04Q 20 D04 21 D03Q 22 D03 23 VEE 24 VCCD 25 VEE 26 D02Q 27 D02 28 D01Q 29 D01 30 D00Q 31 D00 32 VCCD 33 PICLKQ 34 PICLK 35 VCCD 36 PARITYQ 37 PARITY 38 POCLKQ 39 POCLK 40 VCCD 41 CREFQ 42 CREF 43 PARINV 44 MUXR1 45 MUXR0 46 PRSCLOQ 47 PRSCLO 48 TZA3017HW 78 DINQ 97 D14 95 D15 84 INT MGW560 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The TZA3017HW converts parallel data into a serial bit stream with a maximum line rate of 3.2 Gbits/s. A multiplexing ratio of 4 : 1, 8 : 1 or 16 : 1 can be selected. For 8B/10B encoded protocols (e.g. Gigabit Ethernet), a multiplexing ratio of 10 : 1 is supported. The IC contains a clock synthesizer that synchronizes the internal oscillator to an external reference frequency. Configuring the TZA3017HW by I2C-bus or external pins The IC features two types of user interface: I2C-bus or direct programming of eight pre-defined modes. Interface selection is set by pin UI (user interface); see Table 1. The I2C-bus mode is operational if pin UI is left open or connected to VCC. If pin UI is connected to VEE, pins DR0, DR1 and DR2 are available for selection of eight pre-programmed modes. 6 2002 Jan 16 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 1 PIN UI 0 1 Truth table for UI MODE pre-programmed I2C-bus control PIN 54 DR0 CS PIN 53 DR1 SDA PIN 52 DR2 SCL TZA3017HW The bit rates in Table 3 assume a reference frequency of 19.44 MHz applied to pins CREF and CREFQ. After power-up, the TZA3017HW initiates a Power-On Reset (POR) sequence to restore the default settings of the I2C-bus registers, regardless of the programming mode. For the defaults; see Table 10. Clock synthesizer The clock synthesizer is a fractional N type of synthesizer, and consists of a Voltage Controlled Oscillator (VCO), several dividers, a Phase Frequency Detector (PFD), an integrated loop filter, a lock detection circuit and a prescaler output buffer; see Fig.3. The internal VCO is phase-locked to the reference clock signal provided at pins CREF and CREFQ. This frequency is typically 19.44 MHz. Because of the 22 bits fractional N capability, any combination of line rate and reference frequency between 18 and 21 MHz is possible. The LSB (bit k[0]) of the fractional divider, should be set to logic 1 to avoid limit cycles. These are cycles of less than maximum length, which generate spurs in the frequency spectrum. This leaves 21 bits (k[21:1]) available for programming the fraction, allowing approximately 10 Hz of frequency resolution without altering the reference frequency. To meet most transmission standards, the reference frequency should be very accurate. In order to be able to synthesize a clean RF clock, that is compliant with the most stringent jitter generation requirements, it should also be very clean in terms of phase noise; see Section "Jitter performance". All parts of the Phase-Locked Loop (PLL) are internal; no external components are required. This allows for easy application. In I2C-bus mode, the chip is configured by using the I2C-bus connections (SDA and SCL). The Chip Select pin CS has to be HIGH during I2C-bus read or write actions. When pin CS is set LOW, the programmed configuration remains active, but signals SDA and SCL are ignored. In this way, all ICs in the application with the same I2C-bus addresses (e.g. other TZA3017) are individual accessible. The I2C-bus address is given in Table 2. Table 2 A6 1 I2C-bus address of the TZA3017HW A5 0 A4 1 A3 0 A2 1 A1 0 A0 0 R/W X A detailed list of all I2C-bus registers and the meaning of their contents can be found in Chapter "I2C-bus registers". Some functions in the TZA3017HW are controllable by using a pin or the I2C-bus. In these cases an extra I2C-bus bit, called I2C 2002 Jan 16 7 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW handbook, full pagewidth REFERENCE DIVIDER LOL up down VCO OCTAVE DIVIDER CHARGE-PUMP AND LOOP FILTER CREF CREFQ /R PHASEFREQUENCY DETECTOR /M to MUX MAIN DIVIDER PRSCLO PRSCLOQ /N 9 FRACTION CALCULATOR 9 N [0:8] 22 K [0:21] MGW561 Fig.3 Schematic diagram of the clock synthesizer. 2002 Jan 16 8 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Programming the clock synthesizer Programming the clock synthesizer involves four dividers: the reference (frequency) divider R, the main divider N, the fractional divider K and the octave divider M. The first step is to determine in which octave the desired bit rate fits. Figure 4 together with Tables 4 and 5 assists in finding the correct octave. The value for R is usually 1; see Section "Programming the reference clock" for detailed information. Once the octave and the reference frequency are known, the main division ratio N and the fractional part K, can be calculated according to the flowchart in Fig.5. Four examples are given. Table 4 Octave definition M 1 2 4 8 16 32 64 LOWEST BIT RATE (Mbits/s) 1800 900 450 225 112.5 56.25 28.125 HIGHEST BIT RATE (Mbits/s) 3200 1800 900 450 225 112.5 56.25 Table 5 TZA3017HW List of most common optical transmission protocols LINE RATE (Mbits/s) 3125.00 2970.00 2666.06 2488.32 2380.00 2125.00 1485.00 1380.00 1300.00 1250.00 1062.50 1062.50 1062.50 622.08 595.00 425.00 265.63 212.50 200.00 155.52 125.00 125.00 106.25 OCTAVE NUMBER 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 3 3 4 4 4 4 4 5 PROTOCOL 10GE 2xHDTV STM16/OC48 +FEC STM16/OC48 DV-6000 Fibre Channel HDTV D-1 Video DV-6010 Gigabit Ethernet Fibre Channel OptiConnect ISC STM4/OC12 DV-6400 Fibre Channel OptiConnect Fibre Channel ESCON/SBCON STM1/OC3 FDDI Fast Ethernet Fibre Channel OCTAVE 0 1 2 3 4 5 6 6 handbook, halfpage 5 4 3 2 1 0 28.125 56.25 112.5 225 450 900 1800 3600 MGT824 f (Mbits/s) Fig.4 Commonly used line rates and allocation of octaves along a logarithmic bit rate scale. 2002 Jan 16 9 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW handbook, full pagewidth CALCULATE BIT RATE n, k = bit rate x M x R f ref n is integer part k is fractional part yes k=0? no NILFRAC = 1 NILFRAC = 0 no no no 0.25 < k < 0.75 yes k 0.25 ? yes k 0.75 ? yes k = k + 0.5 N=2xn N=2xn N=2xn-1 k = k - 0.5 N=2xn+1 j = 21 k=kx2 no k1? yes Kj = 1 k=k-1 Kj = 0 decimal to binary conversion of fractional part j=j-1 j=0? yes K0 = 1 no Write K j into register #B3, #B4 and #B5 Convert N to binary and write into register #B1, and #B2 END MGW570 Fig.5 Flowchart to calculate N and K for the required bit rate. 2002 Jan 16 10 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW Example 1: An SDH or SONET link has a line rate of 2488.32 Mbits/s (STM16/OC48) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF and CREFQ is 77.76 MHz. This means that the reference division R needs to be 4; see Section "Programming the reference clock". The values of n and k can 2488.32 Mbits/s x 1 x 4 bit rate x M x R be calculated from the flowchart: n = --------------------------------------- = ------------------------------------------------------------ = 128 77.76 MHz f ref Since k = 0 in this example, no fractional functionality is required, and bit NILFRAC should be logic 1 (register B3H). N = 2 x n and no correction is required. Consequently the appropriate values are: R = 4 (register B6H), M = 1 (register B0H) and N = 256 (registers B1H and B2H). Example 2: An SDH STM16 or SONET OC48 link with FEC, has a line rate of 2666.057143 Mbits/s (15/14 x 2488.32 Mbits/s) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF and CREFQ is 38.88 MHz. This means that the reference division R, needs to be 2. Calculate n bit rate x M x R 2666.05714283 Mbits/s x 1 x 2 and k from the flowchart: n = --------------------------------------- = -------------------------------------------------------------------------------- = 137.1428571 f ref 38.88 MHz This means that n = 137, k = 0.1428571 and bit NILFRAC should be logic 0 (register B3H). Since k < 0.25, k is corrected to 0.6428571, while the corrected N becomes N = 273. Consequently the appropriate values are: R = 2 (register B6H), M = 1 (register B0H), N = 273 (registers B1H and B2H) and K = 10 1001 0010 0100 1001 0011 (registers B3H, B4H and B5H). The FEC bit rate is usually quoted to be 2666.06 Mbits/s. Due to round off errors, this leads to a slightly different value for k than in the example. Example 3: A fibre channel link has a line rate of 1062.50 Mbits/s and consequently fits in octave number 1, so M = 2. Suppose the reference frequency provided at pins CREF and CREFQ, is 19.44 MHz. This means that the reference division R needs to be 1. Calculate n and k from the flowchart: bit rate x M x R 1062.50 Mbits/s x 2 x 1 n = --------------------------------------- = ------------------------------------------------------------ = 109.3106996 f ref 19.44 MHz This means that n = 109, k = 0.3107 and bit NILFRAC should be logic 0 (register B3H). Since k is between 0.25 and 0.75, k does not need to be corrected and N = 2 x n = 218. Consequently the appropriate values are: R = 1 (register B6H), M = 2 (register B0H) and N = 218 (registers B1H and B2H). K = 01 0011 1110 0010 1000 0001 (registers B3H, B4H and B5H). Example 4: A non standard transmission link has a line rate of 3012 Mbits/s and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF and CREFQ, is 20.50 MHz. This means that the reference division R needs to be 1. Calculate n and k from the 3012 Mbits/s x 1 x 1 bit rate x M x R flowchart: n = --------------------------------------- = ---------------------------------------------------- = 146.9268293 20.50 MHz f ref This means that n = 146, k = 0.9268293 and bit NILFRAC should be logic 0 (register B3H). Since k is larger than 0.75, k needs to be corrected to 0.4268293 and N = 2 x n + 1 = 293. Consequently the appropriate values are: R = 1 (register B6H), M = 1 (register B0H) and N = 293 (registers B1H and B2H). K = 01 1011 0101 0001 0010 1011 (registers B3H, B4H and B5H). If the I2C-bus is not used, switching the clock synthesizer to eight pre-programmed line rates is possible by using pins DR0, DR1 and DR2; see Table 3. 2002 Jan 16 11 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Programming the reference clock Normal operation in an SDH/SONET application assumes the use of a 19.44 MHz reference clock connected to pins CREF and CREFQ. However, the use of any reference frequency between 18 and 21 MHz is allowed. By using the I2C-bus, a wider range of clock frequencies can be used by programming R through bits REFDIV in register B6H; see Table 6. Internally, the reference frequency is always divided to the lowest range, from 18 to 21 MHz. For SDH/SONET applications, this would be19.44 MHz. Table 6 Truth table for the REFDIV bits SDH/SONET REFERENCE FREQUENCY 19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz REFERENCE FREQUENCY RANGE 18 to 21 MHz 36 to 42 MHz 72 to 84 MHz 144 to 168 MHz Parallel bus clocking schemes TZA3017HW register". On demand it generates an interrupt signal at pin INT; see Section "Interrupt generation". Jitter performance The clock synthesizer of the TZA3017HW has been optimized for lowest jitter generation. For all SDH/SONET line rates, the jitter generation is compliant with ITU-T standard G.958, provided the reference clock is clean enough. For optimum jitter generation, the single sideband phase noise of the reference frequency should be less than -140 dBc/Hz, for frequencies greater than 12 kHz from the carrier. If the reference divider R is used, this requirement eleviates with approximately 20 x log (R). Multiplexer The multiplexer comprises a high-speed input register, a 4-bit deep First In First Out (FIFO) elastic buffer, a parity check circuit and the actual multiplexing tree. DIVISION REFDIV FACTOR R 00 01 10 11 1 2 4 8 Prescaler output The prescaler output (PRSCLO and PRSCLOQ) is always a measure of the internal frequency of the clock synthesizer. It is the VCO frequency divided by the main division factor. If the synthesizer is in-lock, the frequency is equal to the reference frequency at CREF and CREFQ divided by R. This forms an accurate reference for another PLL. If needed, bit PRSCLINV from register C8H, can invert the output of the prescaler. If no prescaler information is desired, bit PRSCLEN from the same register can disable the output. Apart from these settings, the type of output, the termination mode and the signal amplitude can be set. These parameters follow the settings of the parallel multiplexer output clock (POCLK and POCLKQ) and parity error output (PARERR and PARERRQ). For programming details, see Section "Configuring the parallel bus". Loss Of Lock (LOL) During normal operation, the Loss Of Lock output (pin LOL) should be LOW. In this event the clock synthesizer is in-lock, and the output frequency corresponds to the programmed value. If pin LOL goes HIGH, phase and/or frequency lock is lost, and the output frequency may deviate from the programmed value. The LOL condition is also available in I2C-bus registers INTERRUPT and STATUS; see Sections "Interrupt register" and "Status 2002 Jan 16 12 The TZA3017HW supports both co-directional and contra-directional clocking schemes for the parallel data bus; see Figs. 6 and 7. Pin CLKDIR or I2C-bus bit CLKDIR in register MUXCNF1 (register A1H), alters the clocking scheme. A HIGH level on pin CLKDIR or I2C-bus bit CLKDIR selects co-directional clocking, which is default. In the co-directional application, the clock is provided on pins PICLK and PICLKQ and the data on D00/D00Q to D15/D15Q. POCLK and POCLKQ is available if necessary, but can be disabled by I2C-bus bit POCLKEN (register A1H). In a contra-directional clock application, no clock is provided on pin PICLK. The clock that samples the input data on the parallel bus is an internal clock derived from POCLK. In this application, the part providing the parallel data has to be clocked with the POCLK/POCLKQ clock. In order to alleviate timing problems, the phase of POCLK, with respect to the internal clock, can be shifted in 90 degree steps. I2C-bus bit POCLKINV (180 degrees) together with bit POPHASE (90 degrees), set the phase shift; see Table 7. Both bits are located in register A1H. Table 7 Truth table for the POCLKINV and POPHASE bits POPHASE 0 1 0 1 PHASE SHIFT 0 90 180 270 POCLKINV 0 0 1 1 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW handbook, full pagewidth FRAMER TZA3017HW PARITY PARITYQ 16 D00 to D15 D00Q to D15Q PICLK PICLKQ POCLK POCLKQ FIFORESET CREF MGW565 TX_PARITY TX_DATA 16 TX_CLK TX_CLK_SRC system clock Fig.6 Co-directional clocking diagram. handbook, full pagewidth FRAMER TZA3017HW PARITY PARITYQ 16 D00 to D15 D00Q to D15Q TX_PARITY TX_DATA 16 TX_CLK_SRC POCLK POCLKQ FIFORESET CREF MGW566 system clock Fig.7 Contra-directional clocking diagram. 2002 Jan 16 13 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter FIFO In the co-directional clocking scheme, the input register samples the parallel bus data on the rising edge of PICLK/PICLKQ. The same clock writes this data into the FIFO. Data is retrieved from the FIFO by an internal clock, derived from the clock generator of the actual multiplexing tree. This provides for large jitter tolerance on the parallel interface; the FIFO absorbs momentary phase perturbations. Excessively large phase perturbations might stretch the elastic buffer to its limits, causing a FIFO over or underflow. Pin OVERFLOW and I2C-bus registers INTERRUPT and STATUS indicate this situation; see Sections "Interrupt register" and "Status register". On demand it generates an interrupt signal at pin INT; see Section "Interrupt generation". The overflow alarm persists until the FIFO is reset by a HIGH level on pin FIFORESET or by I2C-bus bit FIFORESET in register MUXCNF0 (register A2H). FIFORESET also initializes the FIFO. To fully benefit from the FIFO, it should be reset whenever there has been a Loss Of Lock condition, or when bit rates have changed. The asynchronous FIFORESET signal is re-timed by the internal clock from the clock generator. Two clock cycles after FIFORESET has been made HIGH, the FIFO initializes. Two clock cycles after FIFORESET has been made LOW, the FIFO will be operational again. To initialize automatically, when an overflow has occurred, it is possible to connect pin OVERFLOW directly to pin FIFORESET. Table 8 Setting the multiplexing ratio PIN MUXR0 0 1 0 1 BIT MUXR (REG 21H) 00 01 10 11 MULTIPLEXING RATIO 4:1 8:1 10 : 1 16 : 1 Adjustable multiplexing ratio TZA3017HW Pins MUXR0 and MUXR1 or bits MUXR in I2C-bus register MUXCNF1 (register A1H), configure the multiplexing ratio of the TZA3017HW. The parallel input bus is always centred around the middle (pin VEE) for optimum layout connectivity. Table 8 lists the active inputs for the various multiplexing ratios. In I2C-bus mode, the 16 : 1 ratio is default. In 16 : 1 mode, D00/D00Q is the LSB, in 10 : 1 mode, D03/D03Q is the LSB, in 8 : 1 mode, D04/D04Q is the LSB and in 4 : 1 mode D06/D06Q is the LSB. Unused inputs are disabled. For multiplexing ratios of 4 : 1, 8 : 1 and 16 : 1, the MSB is transmitted first. In 10 : 1 multiplexing mode, the LSB is transmitted first. I2C-bus bit BUSSWAP in register MUXCNF2 (A0H), changes the bus order. Bit BUSSWAP simply reverses the order of bits from MSB to LSB or vice versa, to allow for optimum layout connectivity. The highest supported parallel bus speed is 400 Mbits/s. Therefore the 4 : 1 multiplexing ratio is only supported for line rates up to 1.6 Gbits/s. PIN MUXR1 0 0 1 1 ACTIVE INPUT PINS D06 to D09 D04 to D11 D03 to D12 D00 to D15 (all) 2002 Jan 16 14 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Parity checking In order to check the integrity of the data provided on the parallel input bus, a parity checking function has been implemented in the IC. The calculated parity, based on the data currently on the bus, is compared to the expected parity provided at pins PARITY and PARITYQ. If these do not match, i.e. a parity error has occurred, the PARERR and PARERRQ outputs are HIGH during the next parallel bus clock period (PICLK period). The type of parity, odd or even, can be set by pin PARINV or via I2C-bus bit PARINV (register A0H). A LOW level corresponds with even parity, which is default for I2C-bus bit PARINV. Configuring the parallel bus Several options exist that allow flexible configuration of the parallel bus and associated inputs and outputs. For the outputs the configuration options are; output driver type, termination mode, output amplitude, signal polarity and selective enabling or disabling of various outputs. These options are set in registers MUXCNF1 (A1H) and IOCNF2 (C8H). The output pins affected by these registers are POCLK/POCLKQ, PARERR/PARERRQ and PRSCLO/PRSCLOQ. Bit MFOUTMODE selects the CML or LVPECL output driver (default LVPECL). Bit MFOUTTERM sets the termination mode to standard LVPECL or floating termination, or, in case of CML, to DC or AC-coupled. The four MFS bits adjust the amplitude in all cases. The default output amplitude is 800 mV (p-p) single-ended. Bit PDINV inverts the polarity of the parallel data and PICLKINV inverts the co-directional input clock, effectively shifting the clock edge by half a clock cycle, and changing the rising edge into a falling edge. This might resolve a parallel bus timing problem. Both bits are accessible in register MUXCNF2 (register A0H). Rail-to-rail parallel data and clock inputs The differential parallel data and clock inputs, D00/D00Q to D15/D15Q, PARITY/PARITYQ and PICLK/PICLKQ, handle any input swing with a minimum of 50 mV single-ended. The inputs accept any value between VEE and VCC, i.e. the input buffers are true rail-to-rail. The maximum current flowing into the pins and power dissipation generated by the input current, limit the maximum voltage swing. A differential hysteresis of 25 mV is implemented. I2C-bus bit PIHYST in register MUXCNF0 (register A2H) switches the hysteresis. The default setting for the hysteresis is only active in LVDS mode. 2002 Jan 16 15 Loop mode I/Os TZA3017HW In order to reduce the number of external components, internal termination is provided for the most common standards, such as LVPECL, CML and LVDS. Pins MD0 and MD1 determine the termination mode. Table 9 lists the supported options. Table 9 Input termination mode selection PIN MD0 0 1 0 1 MODE floating LVDS CML LVPECL TERMINATION 100 differential 100 differential (hysteresis on) 50 to VCC 50 to VCC - 2 V PIN MD1 0 0 1 1 As indicated in Fig.1, it is possible to use the IC for loop back purposes. A `line loop back' is possible by setting pin ENLINQ to LOW. In this case, instead of taking the input from the multiplexer, the switch will select inputs DIN/DINQ and CIN/CINQ. Setting pin ENLOUTQ to LOW activates the `diagnostic loop back' mode. In this case, the synthesized clock and serial data will be available both at the normal RF outputs (pins DOUT/DOUTQ and COUT/COUTQ) and at the loop mode output (pins DLOOP/DLOOPQ and CLOOP/CLOOPQ). I2C-bus bits ENLOUT and ENLIN in register MUXCNF2 (register A0H) also sets these two loop modes. Configuring the RF I/Os The polarity of the individual serial data and clock I/Os can be inverted via the I2C-bus. The position of the data and clock outputs (or inputs) can also be swapped. This solves connection problems with other ICs. Registers IOCNF0 (CBH) and IOCNF1 (CAH) program all RF I/O configurations. When the RF input data and clock are swapped by means of bit CDINSWAP (register CAH), the signals present at pins CIN and CINQ are assumed to be data and the signals at pins DINQ and DIN are assumed to be clock. The same holds for swapping the RF outputs. By means of bit CDOUTSWAP (register CAH), normal mode data is present at pins COUTQ and COUT and clock at pins DOUTQ and DOUT. By means of bit CDLOOPSWAP (register CBH), the loop mode data output is present at pins CLOOPQ and CLOOP and clock at pins DLOOPQ and DLOOP. Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter I2C-bus bits DOUTENA and COUTENA (register CAH), independently disable normal mode outputs at pins DOUT/DOUTQ and COUT/COUTQ The RF CML outputs have an (in 16 steps) adjustable signal amplitude between 62.5 mV (p-p) and 1000 mV (p-p) single-ended, controlled by bits RFS (register CBH). The default amplitude is 250 mV (p-p) single-ended. I2C-bus bit RFOUTTERM determines the termination scheme to be either DC or AC-coupled (DC-coupled is default). CMOS control inputs Most CMOS control inputs have an internal pull-up resistor. An open connection equals a HIGH input. Only the LOW state needs to be actively forced. This holds for pins UI, MUXR0, MUXR1, PARINV, CLKDIR, ENLOUTQ, ENLINQ, MD0, MD1, FIFORESET and CS. The same is true for pins DR0, DR1 and DR2 in pre-programmed mode (pin UI = LOW). In I2C-bus mode (pin UI = HIGH), pins SCL and SDA comply with the I2C-bus interface standard. Power supply connections Four separate supply domains (VDD, VCCD, VCCO and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC via separate filters. All supply pins, including the exposed die pad, must be connected. The die pad should be connected to ground with an as low as possible inductance. Since the die pad is also used as the main ground return of the chip, the connection should also have a low DC impedance. The voltage supply levels should be in accordance with the values specified in Chapters "Characteristics" and "Limiting values". All external components should be surface mounted devices, preferably of size 0603 or smaller. The components have to be mounted as closely to the IC as possible. Interrupt register TZA3017HW The TZA3017HW INTERRUPT register (00H), reports the status of several alarm and mode indication flags; temperature alarm, loss of lock condition of the clock synthesizer and an overflow condition of the FIFO. An I2C-bus read action of register 00H, polls the interrupt register. The read action resets all status flags. If the alarm is still present, the interrupt flag is immediately set. Status register The TZA3017HW STATUS register (01H), holds the same content as the interrupt register, but reports the current status. i.e. without a memory function as used in the interrupt register. An I2C-bus read action of register 01H, polls the status register. Interrupt generation The TZA3017HW features a fully configurable interrupt generator, based on the interrupt flags (register 00H). Register INTMASK (register CCH) determines the masking of the status bits generating an interrupt. The MSB of register INTMASK determines the output type of pin INT. The choices are standard CMOS output or open-drain outputs. The latter is the default value. I2C-bus bit INTPOL in the same register, determines the polarity of pin INT. The interrupt output is inverted as default, i.e. an interrupt will pull the output LOW. Together with the selected open-drain output, this set-up allows several receivers to be connected to a common interrupt wire. Only one 3.3 k pull-up resistor is required. When an interrupt occurs, the status of the receiver is available at the INTERRUPT register (00H). An I2C-bus read action resets the interrupt register. I2C-bus registers Setting pin UI HIGH or leaving the pin open-circuit, allows I2C-bus programming. The I2C-bus registers can be accessed via the 2-wire I2C-bus interface (pins SCL and SDA), if pin CS (Chip Select) is HIGH during read or write actions. Table 10 shows the I2C-bus register list. 2002 Jan 16 16 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 10 I2C-bus register list ADDRESS 00H 01H A0H A1H A2H B0H B1H B2H B3H B4H B5H B6H C8H CAH CBH CCH NAME INTERRUPT STATUS MUXCNF2 MUXCNF1 MUXCNF0 DIVCNF MAINDIV1 MAINDIV0 FRACN2 FRACN1 FRACN0 SYNTHCNF IOCNF2 IOCNF1 IOCNF0 INTMASK FUNCTION Interrupt register; see Table 11 for explanation Status register; see Table 12 for explanation Multiplexer configuration register 2; see Table 13 for explanation Multiplexer configuration register 1; see Table 14 for explanation Multiplexer configuration register 0; see Table 15 for explanation Octave and loop mode configuration register; see Table 16 for explanation Main divider division ratio N (MSB); see Table 17 for explanation Main divider division ratio N; see Table 18 for explanation Fractional divider division ratio K; see Table 19 for explanation Fractional divider division ratio K; see Table 20 for explanation Fractional divider division ratio K; see Table 21 for explanation Synthesizer configuration register; see Table 22 for explanation I/O configuration register 2; parallel outputs; see Table 23 for explanation I/O configuration register 1; RF serial I/Os; see Table 24 for explanation I/O configuration register 0; RF serial I/Os; see Table 25 for explanation Interrupt masking register; see Table 26 for explanation TZA3017HW DEFAULT RANGE n.a. n.a. 0000 0000 0110 1001 0000 0000 0000 0000 0000 0001 0000 0000 1000 0000 0000 0000 0000 0001 0000 0000 0010 1100 1100 0000 0000 0011 0101 0000 n.a. n.a. n.a. n.a. (128 to 511) n.a. n.a. n.a. n.a. n.a. 2002 Jan 16 17 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 11 Register INTERRUPT (address: 00H) BIT 7 6 5 4 3 2 1 1 0 x 1 0 1 0 0 0 x x Temperature alarm junction temperature 140 C junction temperature < 140 C FIFO over or underflow: FIFO over or underflow occurred FIFO normal operation 0 PARAMETER DESCRIPTION Loss Of Lock (LOL) synthesizer out of lock (loss of lock condition) synthesizer in lock TZA3017HW NAME LOL reserved TALARM OVERFLOW reserved Table 12 Register STATUS (address: 01H) BIT 7 6 5 4 3 2 1 1 0 x 1 0 1 0 0 0 x x Temperature alarm junction temperature 140 C junction temperature < 140 C FIFO over or underflow FIFO over or underflow occurred FIFO normal operation reserved OVERFLOW 0 PARAMETER DESCRIPTION Loss Of Lock (LOL) synthesizer out of lock (loss of lock condition) synthesizer in lock reserved TALARM LOL NAME 2002 Jan 16 18 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 13 Register MUXCNF2 (address: A0H, default value: 00H; see also last row of table) BIT 7 6 5 4 3 2 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 PARAMETER DESCRIPTION Parallel bus swapping D0 = MSB, D15 = LSB (swapped) D15 = MSB, D0 = LSB (normal) Parity checking odd parity even parity Parity programming through I2C-bus interface through external pin PARINV Parallel clock input polarity inverted normal Parallel data input polarity inverted normal Enable loop mode inputs loop mode inputs enabled loop mode inputs disabled Enable loop mode outputs loop mode outputs enabled loop mode outputs disabled Loop mode control through I2C-bus interface through external pins ENLINQ and/or ENLOUTQ TZA3017HW NAME BUSSWAP PARINV I2CPARINV PICLKINV PDINV ENLIN ENLOUT I2CLOOPMODE default value 2002 Jan 16 19 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 14 Register MUXCNF1 (address: A1H, default value: 69H; see also last row of table) BIT 7 6 5 4 3 2 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 enabled disabled Parallel clock output phase 90 phase shift 0 phase shift Parallel clock output polarity inverted normal Parallel clock direction co-directional clocking contra-directional clocking Parallel clock direction programming through I2C-bus interface through external pin CLKDIR Multiplexing ratio 16 : 1 10 : 1 8:1 4:1 Multiplexing ratio programming through I2C-bus interface through external pins MUXR0 and MUXR1 PARAMETER DESCRIPTION Parallel clock output enable TZA3017HW NAME POCLKEN POPHASE POCLKINV CLKDIR I2CLKDIR MUXR I2CMUXR default value 2002 Jan 16 20 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 15 Register MUXCNF0 (address: A2H, default value: 00H; see also last row of table) BIT 7 6 5 4 3 2 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO reset reset FIFO normal mode FIFO reset programming through I2C-bus interface through external pin FIFORESET Parallel input hysteresis hysteresis with every input mode hysteresis only in LVDS mode PARAMETER DESCRIPTION TZA3017HW NAME FIFORESET I2CFIFORESET PIHYST reserved default value Table 16 Register DIVCNF (address: B0H, default value: 00H; see also last row of table) BIT 7 6 5 4 3 2 1 0 PARAMETER DESCRIPTION Division ratio octave divider M; octave selection 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 M = 1, octave number 0 M = 2, octave number 1 M = 4, octave number 2 M = 8, octave number 3 M = 16, octave number 4 M = 32, octave number 5 M = 64, octave number 6 reserved default value NAME DIV_M Table 17 Register MAINDIV1 (address: B1H, default value: 01H; see also last row of table) BIT 7 0 0 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 1 0 N8 PARAMETER DESCRIPTION Division ratio divider N: N8 = MSB NAME DIV_N default value Table 18 Register MAINDIV0 (address: B2H, default value: 00H; see also last row of table) BIT 7 N7 0 0 6 N6 0 5 N5 0 4 N4 0 3 N3 0 2 N2 0 1 N1 0 21 0 N0 PARAMETER DESCRIPTION Division ratio divider N: N0 = LSB NAME DIV_N default value 2002 Jan 16 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 19 RegisterFRACN2(address: B3H, default value: 80H; see also last row of table) BIT 7 x 1 0 1 0 0 0 0 0 0 0 6 5 K21 4 K20 3 K19 2 K18 1 K17 0 K16 PARAMETER DESCRIPTION Fractional divider K: K21 = MSB NILFRAC control bit (NF) no fractional N functionality fractional N functionality TZA3017HW NAME DIV_K NILFRAC default value Table 20 RegisterFRACN1(address: B4H, default value: 00H; see also last row of table) BIT 7 K15 0 0 6 K14 0 5 K13 0 4 K12 0 3 K11 0 2 K10 0 1 K9 0 0 K8 PARAMETER DESCRIPTION Fractional divider K NAME DIV_K default value Table 21 RegisterFRACN0(address: B5H, default value: 00H; see also last row of table) BIT 7 K7 0 0 6 K6 0 5 K5 0 4 K4 0 3 K3 0 2 K2 0 1 K1 1 0 K0 PARAMETER DESCRIPTION Fractional divider K: K0 = LSB NAME DIV_K default value Table 22 Register SYNTHCNF (address: B6H, default value: 00H; see also last row of table) BIT 7 6 5 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 4 0 3 0 2 0 1 0 Synthesizer manual initialization toggle to initialize synthesizer normal operation; auto initialize Reference frequency divider R = 8; Reference frequency = 155.52 MHz R = 4; reference frequency = 77.76 MHz R = 2; reference frequency = 38.88 MHz R = 1; reference frequency = 19.44 MHz default value REFDIV 0 PARAMETER DESCRIPTION NAME reserved INITSYNTH 2002 Jan 16 22 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 23 Register IOCNF2 (address: C8H, default value: 2CH) BIT 7 6 5 4 0 1 1 1 0 1 0 1 0 3 0 1 1 2 0 0 1 1 0 0 1 0 PARAMETER DESCRIPTION Parallel output signal amplitude minimum signal level; 60 mV (p-p) default signal level; 800 mV (p-p) maximum signal level; 1000 mV (p-p) Prescaler output polarity inverted normal Prescaler output enable enabled disabled Parallel output termination PECL mode: floating, CML mode: AC-coupled PECL mode: standard, CML mode: DC-coupled Parallel output mode 1 0 0 0 1 0 1 1 0 0 CML; Current Mode Logic PECL; Positive Emitter Coupled Logic TZA3017HW NAME MFS PRSCLINV PRSCLEN MFOUTTERM MFOUTMODE default value 2002 Jan 16 23 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 24 Register IOCNF1 (address: CAH, default value: C0H; see also last row of table) BIT 7 6 5 4 3 2 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 inverted normal Loop mode data input polarity inverted normal Loop mode input clock and data swap swapped clock and data input pairs normal clock and data input Clock output polarity inverted normal Data output polarity inverted normal Output clock and data swap swapped clock and data output pairs normal clock and data output Clock output enable enabled disabled Data output enable enabled disabled PARAMETER DESCRIPTION Loop mode clock input polarity TZA3017HW NAME CININV DININV CDINSWAP COUTINV DOUTINV CDOUTSWAP COUTENA DOUTENA default value 2002 Jan 16 24 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Table 25 Register IOCNF0 (address: CBH, default value: 03H; see also last row of table) BIT 7 6 5 4 0 0 1 1 0 1 0 1 0 1 0 0 3 0 0 1 2 0 1 1 1 0 1 1 0 PARAMETER DESCRIPTION RF serial output signal amplitude minimum signal level; 60 mV (p-p) default signal level; 250 mV (p-p) maximum signal level; 1000 mV (p-p) Loop mode clock output polarity inverted normal Loop mode data output polarity inverted normal RF serial output termination AC-coupled DC-coupled Loop mode output clock and data swap swapped clock and data output pairs normal clock and data output TZA3017HW NAME RFS CLOOPINV DLOOPINV RFOUTTERM CDLOOPSWAP 0 0 0 0 0 1 1 default value Table 26 Register INTMASK (address: CCH, default value: 50H; see also last row of table) BIT 7 6 5 4 3 2 1 1 0 0 1 0 1 0 1 0 1 0 0 Note 1. Signal is not processed by interrupt controller. 0 0 Mask temperature alarm not masked masked; note 1 Mask OVERFLOW signal not masked masked; note 1 INT output polarity inverted; active LOW output normal; active HIGH output INT output mode standard CMOS output open-drain output 0 0 0 0 0 Mask LOL signal not masked masked; note 1 PARAMETER DESCRIPTION NAME MLOL reserved MTALARM MOVERFLOW INTPOL INTOUT 1 0 1 default value 2002 Jan 16 25 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW WITHOUT USING I2C-BUS Although the TZA3017HW is intended to be programmed via an I2C-bus, a lot of features can be accessed from external pins. This Chapter lists the functions of the TZA3017HW if the User Interface pin (UI) is LOW (no I2C-bus). Features without the I2C-bus (UI = VEE): * 1 of 4 pre-programmed SDH/SONET bit rates; STM1/OC3, STM4/OC12, STM16/OC48, STM16/OC48 +FEC (DR2 to DR0) * 1 of 4 pre-programmed bit rates; Fibre Channel, double Fibre Channel, Gigabit Ethernet, 10-Gigabit Ethernet (DR2 to DR0) * 1 of 4 multiplexing ratios; 16 : 1, 8 : 1, 4 : 1 or 10 : 1 (MUXR1/MUXR0) TZA3017HW * Co-directional or contra-directional clocking scheme (CLKDIR) * Loop mode serial input and output configuration (ENLINQ and ENLOUTQ) * Even/odd parity checking (PARINV) * LVPECL outputs on parallel interface with 1600 mV (p-p) differential signal (DC-coupled termination to VCC - 2 V) * CML serial RF outputs with 500 mV (p-p) differential signal (DC-coupled load) * Loss Of Lock detection (LOL) * FIFO overflow indication * FIFO reset * Temperature alarm (pin INT; open-drain). * Supported reference frequency from 18 to 21 MHz. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCD, VCCA, supply voltage VCCO,VDD Vn DC voltage on pins D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY and PARITYQ VCC - 0.5 VCC + 0.5 POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ UI, CS, SDA, SCL, MUXR0, MUXR1, CLKDIR, PARINV, FIFORESET, MD0, MD1, ENLOUTQ and ENLINQ LOL and OVERFLOW INT In input current on pins D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY and PARITYQ -25 CREF, CREFQ, CIN, CINQ, DIN and DINQ INT Tamb Tj Tstg ambient temperature junction temperature storage temperature -20 -2 -40 -40 -65 +25 +20 +2 +85 +125 +150 mA mA mA C C C VCC - 2.5 VCC + 0.5 -0.5 -0.5 -0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 V V V V V PARAMETER MIN. -0.5 MAX. +3.6 UNIT V THERMAL CHARACTERISTICS In accordance with JEDEC standards JESD51-5 and JESD51-7. SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient; 4 layer printed-circuit board in still air with 36 plated vias connected with the heatsink and the second and fourth ground layer in the PCB VALUE 16 UNIT K/W 2002 Jan 16 26 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW CHARACTERISTICS VCC = 3.14 to 3.47 V; Tamb = -40 to +85 C; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. SYMBOL Supplies ICCA ICCD IDD ICCO ICC(tot) Ptot analog supply current digital supply current digital supply current oscillator supply current total supply current total power dissipation note 1 note 2 note 1 note 2 note 1 note 2 - - - - - - - - - 2.2 205 - 3 29 240 - 0.79 - 2.4 255 365 4 38 300 410 1.05 1.45 mA mA mA mA mA mA mA W W PARAMETER CONDITIONS MIN TYP MAX UNIT CMOS input; pins UI, DR0, DR1, DR2, CS, MUXR0, MUXR1, MD0, MD1, ENLINQ, ENLOUTQ, FIFORESET, PARINV and CLKDIR VIL VIH IIL IIH VOL VOH VOL IOH Vo(p-p) Vo Zo tr tf td(C-D) fDR LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current VIL = 0 V VIH = VCC IOL = 1 mA IOH = -1 mA IOL = 1 mA VOH = VCC - 0.7VCC - - 0 VCC - 0.2 0 - 60 VCC - 2 single-ended to VCC 20% to 80% 80% to 20% between differential cross-overs between differential cross-overs 80 - - -100 40 30 - - - - - - - - - - 100 80 80 - 50 - 0.3VCC - -155 1 V V A A V V CMOS output; pins OVERFLOW, LOL and INT LOW-level output voltage HIGH-level output voltage 0.2 VCC 0.2 10 Open-drain output; pin INT LOW-level output voltage HIGH-level output current V A mV V ps ps ps % Mbits/s Serial output; pins COUT, COUTQ, DOUT, DOUTQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ output voltage swing range single-ended with 50 (peak-to-peak value) external load; note 3 output voltage range output impedance rise time fall time data-to-clock delay duty cycle COUT/COUTQ signal path data rate 1000 VCC 120 - - 100 60 3200 2002 Jan 16 27 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW SYMBOL PARAMETER CONDITIONS MIN - - TYP MAX UNIT Serial input; pins DIN, DINQ, CIN and CINQ Vi(p-p) Vi Zi fDR VI Vi(p-p) Vhys Zi(diff) Zi(se) VT(CML) VT(LVPECL) tSU;CO tHD;CO tSU;CONTRA tHD;CONTRA fpar Vo(p-p) Vo Zo tr tf input voltage (peak-to-peak value) input voltage range input impedance signal path data rate single-ended to VCC single-ended 50 VCC - 1 40 30 VEE - 0.25 single-ended MD1 = LOW; MD0 = HIGH MD1 = LOW MD1 = HIGH 50 25 80 40 - - - 1000 - tbf 40 - 60 VCC - 2 single-ended to VCC 20% to 80% 80% to 20% 80 - - 1000 VCC + 0.25 60 3200 mV V Mbits/s 50 - - - - 100 50 VCC VCC - 2 - - - - 50 - - - 100 250 250 Parallel input (rail-to-rail); pins D00/D00Q to D15/D15Q, PARITY, PARITYQ, PICLK and PICLKQ input voltage range input voltage swing (peak-to-peak value) input differential hysteresis differential input impedance single-ended input impedance VCC + 0.25 1000 - 120 60 - - 0 - tbf - 60 400 V mV mV V V ps ps ps ps % Mbits/s input termination voltage in MD1 = HIGH; CML mode MD0 = LOW input termination voltage in MD1 = HIGH; LVPECL mode MD0 = HIGH set-up time hold time set-up time hold time duty cycle PICLK/PICLKQ parallel bit rate output voltage swing range single-ended with 50 (peak-to-peak value) external load; note 4 output voltage range output impedance rise time fall time co-directional clocking co-directional clocking contra-directional clocking contra-directional clocking between differential cross-overs CML output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ 1000 VCC 120 - - mV V ps ps 2002 Jan 16 28 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW SYMBOL PARAMETER CONDITIONS 50 termination to VCC - 2V 50 termination to VCC - 2V 20% to 80% 80% to 20% MIN VCC - 1.025 - VCC - 1.810 - - - 50 VCC - 1 TYP MAX VCC - 0.880 VCC - 1.620 - - 1000 VCC + 0.25 60 +20 21 UNIT LVPECL output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ VOH VOL tr tf Vi(p-p) Vi Zi fCREF fCREF HIGH-level output voltage LOW-level output voltage rise time fall time V V ps ps 250 250 - - 50 - 19.44 Reference frequency input; pins CREF and CREFQ input voltage (peak-to-peak value) input voltage range input impedance reference clock frequency accuracy reference clock frequency single-ended to VCC SDH/SONET requirement see Section "Programming the reference clock" single-ended mV V ppm MHz 40 -20 18 I2C-bus I/O pins; SCL and SDA VIL VIH Vhys VOL ILI Ci I2C-Timing fSCL tLOW tHIGH tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tr tf SCL clock frequency SCL LOW time SCL HIGH time hold time for START condition set-up time for START condition data hold time data set-up time set-up time for STOP condition SCL and SDA rise time SCL and SDA fall time note 5 note 5 - 1.3 0.6 0.6 0.6 0 100 0.6 20 20 - - - - - - - - - - 100 - - - - 0.9 - - 300 300 kHz s s s s s ns s ns ns LOW-level input voltage HIGH-level input voltage hysteresis of Schmitt trigger inputs LOW-level output voltage input leakage current input capacitance note 5 note 5 IOL = 3 mA; pin SDA open-drain -0.5 0.7VCC 0.05VCC 0 -10 - - - - - - - 0.3VCC VCC - 0.4 +10 10 V V V V A pF 2002 Jan 16 29 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW SYMBOL tBUF Cb tSP VnL VnH Jgen(p-p) PARAMETER bus free time between STOP and START capacitive load on each bus line pulse width of allowable spikes noise margin at LOW-level CONDITIONS 1.3 - note 5 note 5 0 MIN - - - - - TYP - 400 50 - - MAX UNIT s pF ns V V 0.1VCC 0.2VCC noise margin at HIGH-level note 5 PLL characteristics jitter generation (peak-to-peak value) STM1/OC3 mode; note 6 f = 500 Hz to 1.3 MHz f = 12 kHz to 1.3 MHz f = 65 kHz to 1.3 MHz STM4/OC12 mode; note 6 f = 1 kHz to 5 MHz f = 12 kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; note 6 f = 5 kHz to 20 MHz f = 12 kHz to 20 MHz f = 1 to 20 MHz Notes 1. Outputs are not connected. Disabled loop modes, MUX ratio 16 : 1 and default output levels. 2. Outputs are not connected. Enabled loop modes, MUX ratio 16 : 1 and maximum output levels. 3. The output swing is (in 16 steps) adjustable between the min. and max. value, controlled by bits RFS in the I2C-bus register CBH. 4. The output swing is (in 16 steps) adjustable between the min. and max. value, controlled by bits MFS in the I2C-bus register C8H. 5. Guaranteed by design. 6. Reference frequency of 19.44 MHz, with a phase-noise of less than -140 dBc for frequencies of more than 12 kHz from the carrier. - - - - 0.04 - 0.25 0.05 0.05 UI UI UI - - - - - - 0.25 0.05 0.05 UI UI UI - - - - - - 0.25 0.05 0.05 UI UI UI 2002 Jan 16 30 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW handbook, full pagewidth D00 to D15, PARITY t SU;CONTRA valid data t HD;CONTRA POCLK PARERR MGW563 The timing is measured from the cross-over point of the reference signal to the cross-over point of the input. Fig.8 Parallel bus contra-directional timing. handbook, full pagewidth PICLK t HD;CO t SU;CO D00 to D15, PARITY valid data POCLK PARERR MGW562 The timing is measured from the cross-over point of the reference signal to the cross-over point of the input. Fig.9 Parallel bus co-directional timing. 2002 Jan 16 31 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter TZA3017HW handbook, full pagewidth COUT (CLOOP) t d(C-D) DOUT (DLOOP) MGW564 The timing is measured from the cross-over point of the reference signal to the cross-over point of the output. Fig.10 RF output timing. 2002 Jan 16 32 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter PACKAGE OUTLINE HTQFP100: plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm TZA3017HW SOT638-1 c y heatsink side X Dh 75 76 51 50 ZE A e E HE wM bp pin 1 index Lp L detail X Eh A A2 A1 (A3) 100 1 wM ZD 25 bp D HD 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.15 0.85 1.15 0.85 7 0 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 01-03-30 2002 Jan 16 33 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: TZA3017HW * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2002 Jan 16 34 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter Suitability of surface mount IC packages for wave and reflow soldering methods TZA3017HW SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2002 Jan 16 35 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS TZA3017HW Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 Jan 16 36 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter NOTES TZA3017HW 2002 Jan 16 37 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter NOTES TZA3017HW 2002 Jan 16 38 Philips Semiconductors Objective specification 30-3200 Mbits/s fibre optic transmitter NOTES TZA3017HW 2002 Jan 16 39 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/100/01/pp40 Date of release: 2002 Jan 16 Document order number: 9397 750 09169 |
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